1. Field of the Invention
The present invention relates generally to a delay circuit. More particularly, the invention relates to a delay circuit adapted to maintain a constant minimum delay time even where the number of delay blocks in the delay circuit increases, and to delay an input signal only through selected delay blocks.
A claim of priority is made to Korean Patent Application No. 10-2005-0041322, filed May 17, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As the operating speed of semiconductor devices increases, the impact of small differences in a characteristic margin between signals in the semiconductor devices tends to increase accordingly. As a result, semiconductor devices often include a delay circuit having a plurality of delay blocks adapted to precisely control the timing of the signals within a signal path. The delay blocks are controlled by respective control signals to adjust a delay time of the delay circuit, thereby optimizing the characteristic margin between the signals.
FIG. 1 is a block diagram illustrating a conventional delay circuit. Referring to FIG. 1, the delay circuit comprises a plurality of delay blocks 11 through In. The term “block” here simply refers to a portion of the delay circuit. In general, the portion defined by a “block” can be defined by an arbitrary partition of the delay circuit. In addition, the notation “X1Y through XnY” is used throughout this written description to denote first through n-th elements. For example, delay blocks 11 through 1n comprise 1st through n-th delay blocks.
Delay blocks 11 through 1n include respective switches 111 through 1n1, unit delay cells 112 through 1n2, and drivers 113 through 1n3. Delay blocks 11 through 1n are enabled in response to control signals F1 through Fn to delay respective input signals. The input signal for delay block 11 is an input signal “in” and the input signals for respective delay blocks 12 through 1n are output signals of respective previous delay blocks 11 through 1(n−1). Accordingly, input signal “in” is delayed by delay blocks 11 through 1n based on control signals F1 through Fn. Where delay blocks 11 through 1n are disabled according to control signals F1 through Fn, the input signals are transmitted through delay blocks 11 through 11n without delay.
To control whether delay blocks 11 through 1n delay their respective input signals, switches 111 through 1n1 include first transmission paths P111 through P1n1, which are connected directly to drivers 113 through 1n3, and second transmission paths P112 through P1n2, which are connected to drivers 113 through 1n3 via unit delay cells 112 through 1n2. Switches 111 through 1n1 transmit their respective input signals through respective second transmission paths P112 through P1n2 when delay blocks 11 through 1n are enabled, and switches 111 through 1n1 transmit their respective input signals through respective first transmission paths P111 through P1n1 when delay blocks 11 through 1n are disabled.
Unit delay cells 112 through 1n2 are respectively connected to drivers 113 through 1n3 via second transmission paths P112 through P1n2. Unit delay cells 112 through 1n2 delay signals transmitted along second transmission paths P112 through P1n2 by a unit of time and transmit resulting delayed signals to drivers 113 through 1n3. Drivers 113 through 1n3 combine respective signals transmitted through first and second transmission paths P111 through P1n1 and P112 through P1n2 to generate combined signals. Drivers 113 through 1(n−1)3 then transmit the respective combined signals to subsequent delay blocks 12 through 1n. Driver 1n3 transmits its combined signal as an output signal “out”.
Control signals F1 through Fn are typically generated by signal generator using a fuse program or a mode setting operation.
FIG. 2 is a circuit diagram illustrating the delay circuit of FIG. 1 in further detail.
Referring to FIG. 2, switches 111 through 1n1 include inverters I11 through I1n for inverting control signals F1 through Fn and first NAND gates N111 through N1n1 for computing a NAND operation on respective inverted control signals /F1 through /Fn and the respective input signals to delay blocks 11 through 1n and transmitting respective resulting output signals to first transmission paths P1 through P1n1. Switches 111 through 1n1 further include respective second NAND gates N112 through N1n2 for computing a NAND operation on respective control signals F1 through Fn and the respective input signals of delay blocks 11 through 1n and transmitting respective resulting output signals to second transmission paths P112 through P1n2. Unit delay cells 112 through 1n2 include elements (not shown) for delaying an input signal by a predetermined unit of time.
Drivers 113 through 1n3 include respective third NAND gates N113 through N1n3 for computing NAND operations on respective signals transmitted through first and second transmission paths P1 through P1n1 and P112 through P1n2 and transmitting respective resulting output signals to subsequent delay blocks 12 through 1n. 
The operation of the delay circuit of FIG. 2 is explained below with reference to FIG. 3.
In FIG. 3, it is assumed that a delay operation for a particular delay block is enabled when a corresponding control signal has a logic level “high” (denoted “H” in FIG. 3), and the delay operation is disabled when the corresponding control signal has a logic level “low” (denoted “L” in FIG. 3). In FIG. 3, “dn” denotes a delay associated with each NAND gate in FIG. 2, and “du” denotes a delay associated with each unit delay cell 112 through 1n2.
Referring to FIG. 3, control signals F1 through Fn are initially applied to respective delay blocks 11 through 1n with logic level “low”. As a result, the input signals to delay blocks 11 through 1n are delayed as follows.
First delay block 11 receives input signal “in” and generates an inverted input signal /in which is delayed by delay time dn through first NAND gate N111. A resulting output signal from first NAND gate N111 is then input to third NAND gate N111, which further delays the output signal from first NAND gate N111 to generate an input signal for delay block 12, which is delayed by a time a delay time “2dn” relative to input signal “in”. The input signal for delay block 12 is apparent at a node N1. Remaining delay blocks 12 through 1n operate in the same was as delay block 11 to delay their respective input signals by a delay time “2dn” and transmit signals with accumulated delay times to respective nodes N2 through Nn.
As a result, even where delay blocks 11 through 1n are all disabled, input signal “in” is delayed by a delay time “2dn×n” after being transmitted through respective first and third NAND gates N111 through N1n1 and N113 through N1n3 of the first to n-th delay blocks 11 through 1n. In other words, a minimum delay time for the delay circuit is “2dn×n”. Here, the minimum delay time is referred to as a time which the delay circuit delays the input signal in when all of delay blocks 11 through in are disabled.
Referring still to FIG. 3, control signal F1 subsequently transitions to logic level “high” to enable delay block 11. As a result, input signal “in” is delayed as follows.
First delay block 11 receives input signal “in” and generates an inverted input signal /in which is delayed by a delay time “dn+du” through second NAND gate N112 and unit delay cell 112. A resulting output signal from second NAND gate N112 is further delayed by a delay time “2dn+du” through third NAND gate N113, and transmitted to node N1. Since remaining delay blocks 12 through 1n are disabled, they each further delay input signal “in” by a delay time “2dn” and transmit respective output signals with accumulated delay times to nodes N2 to Nn. As a result, the delay circuit delays input signal “in” by an overall delay time “(2dn×n)+du”.
Where the delay circuit enables “m” delay blocks, where m is a natural number greater than 1 and less than or equal to n, the delay circuit delays input signal “in” by a delay time of “(2dn×n)+(du×m)”.
The conventional delay circuit serially connects a plurality of delay blocks and adjusts the number of the enabled delay blocks to delay the input signal by a desired delay time.
However, since the delay circuit contains a plurality of serially connected delay blocks, input signal “in” must be transmitted through all of the delay blocks. Thus, even where the delay circuit does not perform a delay operation, input signal “in” is still transmitted through all of the delay blocks and thus is unnecessarily delayed by the minimum delay time.
In addition, since the minimum delay time increases in proportion to the number of the delay blocks in the delay circuit, the minimum delay time also increases as the number of the delay blocks increases.